EEE 213 • Final • Introduction to Logic Design

Combinational Circuits

Analysis of Circuits

Example - 1

Example - 2

Design of Circuits

Example - 3

Example - 4

Example - 5

Example - 6

Example - 7

Half and Full Adders

Example - 8

Binary Adder

Carry Lookahead Logic

Example - 9

Example - 10

Example - 11

Binary Adder-Subtractor

Example - 12

BCD Adder

Binary Multiplier

Example - 13

Magnitude Comparator

Example - 14

Decoder - 1

Example - 15

Decoder - 2

Example - 16

Example - 17

Example - 18

Example - 19

Example - 20

Encoder

Example - 21

Example - 22

Multiplexer

Example - 23

Example - 24

Example - 25

Example - 26

Introduction

RAM (Random Access Memory)

ROM (Read-Only Memory)

PLA & PAL

Sequential Circuits

SR Latch

SR Latch With Control Input & D Latch

Flip-Flops & D-type Flip-Flops

SR Flip-Flops

JK Flip-Flops & T Flip-Flops

State Table and State Diagram

Analysis Of Clocked Sequential Circuits Part-1

Analysis Of Clocked Sequential Circuits Part-2

Analysis Of Clocked Sequential Circuits Part-3

Analysis Of Clocked Sequential Circuits Part-4

Mealy and Moore Models

State Reduction and Assignment

Design Procedure

Registers

Shift Registers

Serial Adder

Universal Shift Register

Counters - Binary Ripple Counters

Counters - Synchronous Counters

UP-DOWN Binary Counter

Binary Counter With Parallel Load

Other Counters